`timescale 1ns/1ps

module top;

parameter SYSCLK_PERIOD = 10;

reg SYSCLK;
reg NSYSRESET;

initial
begin
    SYSCLK = 1'b0;
    NSYSRESET = 1'b0;
end

/*iverilog */
initial
begin            
    $dumpfile("wave.vcd");        //生成的vcd文件名称
    $dumpvars(0, top);    //tb模块名称
end
/*iverilog */
initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
    #100000
        $stop;
end

always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;

wire scl;
wire sda;
wire ack_error;
wire dev_ack_error;
wire ld_wdata;
reg [7:0] wdata;
reg [7:0] wdata_len;
wire [7:0] rdata;
reg [7:0] rdata_len;
reg [7:0] dev_addr;
wire rdata_vaild;
reg start_signal;
wire transfer_finish;
reg sccb_stop_signal;
wire handle;
reg [4:0] test_flag;
reg [7:0] data_table [0:3];
reg [2:0] byte_cnt;
reg [7:0] rdata_reg [0:1];
always @(posedge SYSCLK or negedge NSYSRESET ) begin
    if(!NSYSRESET)begin
        start_signal <= 'b0;
        test_flag <= 'd0;
        data_table[0] <= 'h11;
        data_table[1] <= 'h22;
        data_table[2] <= 'h33;
        data_table[3] <= 'h44;
        byte_cnt <= 'd0;
        sccb_stop_signal <= 'b0;
    end
    else begin
        sccb_stop_signal <= 'b0;
        start_signal <= 'b0;
        if(test_flag == 'd0) begin
            dev_addr <= 'h50;
            wdata <= data_table[0];
            byte_cnt <= 'd0;
            start_signal <= 'd1;
            wdata_len <= 'd1;
            if(handle) begin
                test_flag <= 'd1;
                start_signal <= 'b0;
            end
        end
        else if(test_flag == 'd1) begin
            start_signal <= 'b0;
            if(ld_wdata)begin
                wdata <= data_table[byte_cnt+'b1];
                byte_cnt <= byte_cnt + 'b1;
                if(byte_cnt == 'd0)begin
                    test_flag <= 'd2;
                end
            end
        end
        else if(test_flag == 'd2) begin
            if(handle == 'b0) begin
                test_flag <= 'd3;
            end
        end
        else if(test_flag == 'd3)begin
            start_signal <= 'b0;
            sccb_stop_signal <= 'b0;
            test_flag <= 'd4;
        end
        else if(test_flag == 'd4) begin
            rdata_len <= 'd2;
            dev_addr <= 'h51;
            start_signal <= 'b1;
            if(handle) begin
                test_flag <= 'd5;
                start_signal <= 'b0;
                byte_cnt <= 'd0;
            end
        end
        else if(test_flag == 'd5) begin
            if(rdata_vaild) begin
                rdata_reg[byte_cnt] <= rdata;
                byte_cnt <= byte_cnt + 'b1;
                if(byte_cnt == 'd1) begin
                    test_flag <= 'd6;
                    sccb_stop_signal <= 'b0;
                end
            end
        end
        else if(test_flag == 'd6) begin
            sccb_stop_signal <= 'b1;
            if(handle == 'b1) begin
                sccb_stop_signal <= 'b0;
                test_flag <= 'd7;
            end
        end
        else begin
        end
    end
    
end
assign sda = (sccb_u0.sda_oe == 'b0) ? 'b1: 'bz;
sccb #(
    .CLK_FREQ(50000000),
    .SCCB_CLK(25000000)
)
sccb_u0 (
    .clk(SYSCLK),
    .rst_n(NSYSRESET),

    .scl(scl),
    .sda(sda),
    .start_signal(start_signal),

    .wdata(wdata),
    .ld_wdata(ld_wdata),
    .wdata_len(wdata_len),
    .ack_error(ack_error),
    .dev_ack_error(dev_ack_error),

    .rdata(rdata),
    .rdata_vaild(rdata_vaild),
    .rdata_len(rdata_len),

    .dev_addr(dev_addr),
    .transfer_finish(transfer_finish),
    .sccb_stop_signal(sccb_stop_signal),
    .handle(handle)
);

endmodule